The present invention relates, in general, to power saving in processor-based systems, and more particularly, to a transition between an active mode and a power-down mode in processor-based systems.
Recently, there has been an increase in the demand for power-saving techniques in processor-based systems such as mobile phones, laptop computers, Personal Digital Assistants (PDAs), cameras, and the like. Power gating is a very effective and widely used power saving technique. In power gating, a state of the processor-based system is saved in a memory and the power supply to at least a part of a processor-based system is cut off. The state of the processor-based system can include the state of the processor, the processor pipelines, the processor registers, the processor peripheral registers, the cache registers, the read-only status registers, the cache state registers, the processor memory, and so forth. The state of the processor-based system can be restored from the memory on the detection of a wake-up event, for example, an interrupt event.
One technique for saving the state of the processor-based system includes software-based save-restore. One prior art application of software-based save-restore technique includes using a Basic Input Output System (BIOS) based save-restore, which is further coupled with a higher level save-restore. The higher level save-restore handles special processor modes such as a user mode and a kernel mode. Another prior art application of software-based save-restore technique includes partitioning the memory into isolated and non-isolated regions. Other techniques include scan-based save-restore and balloon circuit-based state retention.
In existing techniques, once a transition between the active mode and the power-down mode entry is initiated, the processor-based system does not respond to interrupt events. These interrupt events are either explicitly masked off or the transition between the active mode and the power-down mode is triggered by a non-maskable interrupt event, and therefore cannot be interrupted.
Most of the above-mentioned techniques also require significant design changes in the processor-based system. The scan-based save-restore requires design changes to provide an interface between the scan chains and the memory. This technique also requires high-speed scan shifting in order to minimize the time taken for saving and restoring. However, high-speed scan shifting can result in a high current drain. The high current drain can cause electro-migration and degrade the reliability of the processor-based system. The balloon circuit-based save-restore requires the creation of new balloon circuit cell libraries for sequential cells and may also require design changes. Balloon cells are larger in size than regular sequential cells and this may also result in area overheads.
Existing software-based save-restore techniques do not respond to interrupt events once the transition between the active mode and the power-down mode is initiated. This causes delays in the response to interrupt events that arrive after the transition between the active mode and the power-down mode is started. The interrupt events also can be lost if the source of the interrupt events is not available by the time the processor-based system enters the active mode. Further, multiple interrupt events can be served in a different order from the one in which they arrived. In addition, there is an energy overhead associated with the transition between the active mode and the power-down mode when the interrupt events that are wake-up category interrupt events arrive during the transition between active and power-down mode. Moreover, these existing software save-restore techniques do not provide a comprehensive technique for restoration of the read-only registers through software, which can result in incomplete state restoration.